Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
COMPLETE DEPLETION TYPE SOI MOSFET
Document Type and Number:
Japanese Patent JP2005150402
Kind Code:
A
Abstract:

To provide a complete depletion type SOI MOSFET capable of suppressing short channel effect caused by permitting a drain electric field to pass through a BOX layer when the thickness of an SOI layer or the BOX layer is made to be an identical thickness to that of a conventional complete depletion type SOI MOSFET, and of suppressing kink effect.

The complete depletion type SOI MOSFET 11 or 12 is configured such that a p+ region 13A or a p+ region 13B and a p+ region 13C are formed into an L shape from between at least any one of an n+ source region 3 and an n+ drain region 4 and an embedded oxide film layer 2 to an adjacent region of at least any one of the n+ source region 3 and the n+ drain region 4 on the opposite side of the side of a p-channel region 5.


Inventors:
NAKAJIMA YOSHITADA
HANAJIRI TATSURO
TOYABE TATSU
MORIKAWA TAKITARO
SUGANO TAKUO
Application Number:
JP2003385985A
Publication Date:
June 09, 2005
Filing Date:
November 14, 2003
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
UNIV TOYO
International Classes:
H01L29/786; (IPC1-7): H01L29/786
Domestic Patent References:
JPH0394471A1991-04-19
JPS5837966A1983-03-05
JPS6115369A1986-01-23
JPH03296275A1991-12-26
JPH0575119A1993-03-26
Attorney, Agent or Firm:
Toshio Nishizawa