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Title:
COMPLETE SECONDARY SYSTEM DPLL AND DESTUFFING CIRCUIT USING IT
Document Type and Number:
Japanese Patent JPH0884071
Kind Code:
A
Abstract:

PURPOSE: To simultaneously provide a minimum memory capacity and extremely narrow band and short pull-in time in a complete secondary system DPLL.

CONSTITUTION: Two respectively long and short time constants of a primary random walk filter 5 and a secondary random walk filter 6 are prepared, a multilevel phase comparator 4 generates activation signals when a phase error generated when a rapid frequency change is generated exceeds a fixed value and the time constants of the primary random walk filter 5 and the secondary random walk filter 6 are set short by the activation signals. A timer 10 is activated by the activation signals and the time constants of the primary random walk filter 5 and the secondary random walk filter 6 are switched to the long ones when fixed time elapses.


Inventors:
ROKUGO YOSHINORI
ITO MASAAKI
Application Number:
JP21743894A
Publication Date:
March 26, 1996
Filing Date:
September 12, 1994
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03L7/06; H03H17/00; H03L7/093; H03L7/099; H03L7/107; H04J3/07; (IPC1-7): H03L7/06; H03H17/00; H04J3/07
Domestic Patent References:
JPH02280414A1990-11-16
JPH0265314A1990-03-06
JPH01194715A1989-08-04
Attorney, Agent or Firm:
若林 忠



 
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