PURPOSE: To simultaneously provide a minimum memory capacity and extremely narrow band and short pull-in time in a complete secondary system DPLL.
CONSTITUTION: Two respectively long and short time constants of a primary random walk filter 5 and a secondary random walk filter 6 are prepared, a multilevel phase comparator 4 generates activation signals when a phase error generated when a rapid frequency change is generated exceeds a fixed value and the time constants of the primary random walk filter 5 and the secondary random walk filter 6 are set short by the activation signals. A timer 10 is activated by the activation signals and the time constants of the primary random walk filter 5 and the secondary random walk filter 6 are switched to the long ones when fixed time elapses.
ITO MASAAKI
JPH02280414A | 1990-11-16 | |||
JPH0265314A | 1990-03-06 | |||
JPH01194715A | 1989-08-04 |