Title:
COMPOSITION FOR POLISHING SEMICONDUCTOR LAYER
Document Type and Number:
Japanese Patent JP2007180534
Kind Code:
A
Abstract:
To provide a polishing composition by which controlled removal for a silicon oxide-contained layer is possible, because slurries that remove a silicon oxide-containing material at a high removal rates has a tendency to also remove underlying masks and a cap and the uncontrolled removal of these underlying layers has an adverse impact upon final performance of an integrated circuit.
This aqueous polishing composition is useful for polishing a semiconductor substrate. The polishing composition includes 0.05 to 50 wt.% abrasive grains and 0.001 to 2 wt.% λ type carrageenan. The λ type carrageenan has a concentration useful for accelerating TEOS removal rate.
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Inventors:
BIAN JINRU
Application Number:
JP2006335264A
Publication Date:
July 12, 2007
Filing Date:
December 13, 2006
Export Citation:
Assignee:
ROHM & HAAS ELECT MAT
International Classes:
H01L21/304; B24B37/00; C09K3/14
Attorney, Agent or Firm:
Hajime Tsukuni
Koshiro Tsukuda
Fusayuki Saito
Koshiro Tsukuda
Fusayuki Saito