Title:
複合ダイ集積回路パッケージ
Document Type and Number:
Japanese Patent JP2009527130
Kind Code:
A
Abstract:
In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a bottom laminate substrate (BLS) (130) is formed to include interconnection patterns (IP) (170, 172) coupled to a plurality of conductive bumps (PCB) (130). A top substrate (TS) (140) is formed to mount a top package (110) by forming a polyimide tape (PT) (142) affixed to a metal layer (ML) (144), and a top die (136) attached to the ML (144) on an opposite side as the PT (142). A laminate window frame (LWF) (150), which may be a part of the BLS (130), is fabricated along a periphery of the BLS (130) to form a center cavity (160). The center cavity (160) enclosed by the BLS, the LWF and the TS houses the top die (136) affixed back-to-back to a bottom die (134) that is affixed to the BLS (130). The IP (170, 172) formed in the BLS and the LWS (150) provide the electrical coupling between the ML (144), the top and bottom dies (136, 134), and the PCB (130).
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Inventors:
Line, Kevin, Peter
Application Number:
JP2008555485A
Publication Date:
July 23, 2009
Filing Date:
February 15, 2007
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
H01L25/065; H01L25/07; H01L25/18
Attorney, Agent or Firm:
Asamura patent office
Hideto Asamura
Hajime Asamura
Kuniaki Shimizu
Hayashi Zouzo
Takayuki Hatanaka
Akira Iwami
Hideto Asamura
Hajime Asamura
Kuniaki Shimizu
Hayashi Zouzo
Takayuki Hatanaka
Akira Iwami