PURPOSE: To realize micro parallel processing of machine language level by enabling plural instructions to be processed as if they are one compound instruction.

CONSTITUTION: This computer is a compound instruction computer provided with plural arithmetic parts 1 operated in parallel, a register part 2 accessed by them commonly, an operand buffer 3 which performs the read/write of an operand asynchronously with the arithmetic parts and eliminates memory access contention, a memory part 4 divided into banks and interleaved, and an instruction control part 5 which fetches the plural instructions simultaneously from the memory part and checks the contention of the operand and with a feature to execute the plural instructions as one compound instruction.