Title:
COMPOUND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS61189620
Kind Code:
A
Abstract:
PURPOSE:To enable a III-V compound semiconductor layer having reduced distortion in lattices to be formed on an Si substrate, by forming an Si-Ge mixed crystal layer and a single crystal layer each having a thickness smaller than a predetermined value on the substrate such that they are interposed between the substrate and the compound semiconductor layer. CONSTITUTION:A buffer layer 2 is formed on an Si substrate, and a GaAs single crystal layer 3 is provided thereon. The buffer layer 2 has a double structure composed of a first sublayer 2a consisting of Si-Ge mixed crystal and having a thickness of 200Angstrom or less and of a second sublayer 2b of Ge single crystal. The GaAs single crystal layer is caused to epitaxially grow in vapor phase so as to form the compound semiconductor layer 3. According to this method, any distortion in lattices due to a difference in thermal expansion coefficiency between the Si substrate 1 and the compound semiconductor layer 3 can be absorbed.
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Inventors:
OTANI NOBORU
MIYANOCHI MAKOTO
MIYANOCHI MAKOTO
Application Number:
JP2996485A
Publication Date:
August 23, 1986
Filing Date:
February 18, 1985
Export Citation:
Assignee:
SHARP KK
International Classes:
H01L29/812; H01L21/20; H01L21/203; H01L21/205; H01L21/338; (IPC1-7): H01L21/203; H01L21/205; H01L29/80
Attorney, Agent or Firm:
Yoshiro Kurauchi