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Title:
COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS64770
Kind Code:
A
Abstract:

PURPOSE: To form each FET having one kind of an operating layer and to simplify the manufacturing process to a large extent, by arranging the gate electrodes of the field effect transistors in the different orientations in accordance with the magnitudes of threshold voltage values to be controlled, and providing an insulating film or a metal film having stress on the rear surface of a compound semiconductor substrate having the transistors.

CONSTITUTION: Tungsten silicide is deposited on an semi-insulating substrate 5 so as to cover an operating layer 3 to a thickness of 0.5μm by using a sputtering method. Thereafter, the WSi film is patterned into a specified pattern. Thus a Schottky gate 1 is formed. Then, Si ions are implanted. Annealing is performed in an As pressure atmosphere at 750°C for 20 minutes. Thus n+ layers 4a and 4b are formed. A source electrode 2a and a drain electrode 2b comprising metal layers of AuGe-Ni are formed. Finally a W film 6 having a film stress of 2×1010dyn/cm2 is deposited on the entire rear surface of the GaAs substrate to a thickness of 4μm by a sputtering method. An enhancement type FET is obtained from a [011] FET, and a depletion type FET is obtained from a [011] FET.


Inventors:
KANAMORI MIKIO
Application Number:
JP6401587A
Publication Date:
January 05, 1989
Filing Date:
March 20, 1987
Export Citation:
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Assignee:
AGENCY IND SCIENCE TECHN
International Classes:
H01L29/812; H01L21/338; H01L29/04; H01L29/20; H01L29/80; (IPC1-7): H01L29/04; H01L29/20; H01L29/80
Domestic Patent References:
JPS61268070A1986-11-27
JPS61129878A1986-06-17
JPS61115347A1986-06-02
JPS60176276A1985-09-10
JPS5979577A1984-05-08
JPS5923566A1984-02-07
JPS58145168A1983-08-29



 
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