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Patent Searching and Data


Title:
COMPUTATION PROCESSING METHOD FOR INTERFERENCE TORQUE
Document Type and Number:
Japanese Patent JPH08106312
Kind Code:
A
Abstract:

PURPOSE: To level the computing process loads on respective processors by executing an interference torque computing process for one axis by the processor provided corresponding to the axis for driving a link relatively farther from a base side than from the link driven by the former axis.

CONSTITUTION: A computing process for torque τ1cp among computing processes required by the control loop for the axis J1 on the most base side is executed by the processor DPS4 used for the computation required for a 4th loop. The executed computation result of the interference torque τ1cp is sent from the processor DSP4 to a processor DSP1. Similarly, the computing processes for the interference torque values τ2cp and τ2cp of axes J2 and J3 are executed by processors DSP5 and DSP6, whose computation results are sent from the processor DSP5 to the processor DSP2 and from the processor DSP6 to a processor DSP3 and used to generate commands for acceleration/deceleration control over the axes J2 and J3, thereby reducing the computing process loads.


Inventors:
KATO TETSURO
TSUCHIDA YUKINOBU
HATANAKA SHIN
Application Number:
JP26440294A
Publication Date:
April 23, 1996
Filing Date:
October 05, 1994
Export Citation:
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Assignee:
FANUC LTD
International Classes:
B25J9/16; G05B19/18; G05B19/414; (IPC1-7): G05B19/18; B25J9/16; G05B19/414
Attorney, Agent or Firm:
Matsumoto Takemoto (4 outside)