Title:
テストパターン、及び集積回路レイアウトのコンピュータにより具現する設計方法
Document Type and Number:
Japanese Patent JP6951070
Kind Code:
B2
Abstract:
A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.
More Like This:
| JPH07101228 | [Title of Invention] An integrated circuit monitoring device. |
| JPS63214677 | EVALUATING METHOD FOR SEMICONDUCTOR DEVICE |
| JPS63190236 | ELECTRON PROBE ANALYZER |
Inventors:
Yellow
Lee Zheng
Ginger Shu
Lee Zheng
Ginger Shu
Application Number:
JP2016236377A
Publication Date:
October 20, 2021
Filing Date:
December 06, 2016
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H01L21/66; H01L21/3205; H01L21/768; H01L21/82; H01L21/822; H01L23/522; H01L27/04
Domestic Patent References:
| JP2010192521A | ||||
| JP2012234918A | ||||
| JP2005303162A | ||||
| JP8250738A | ||||
| JP5144917A | ||||
| JP2003022946A | ||||
| JP2002026100A | ||||
| JP2000260842A | ||||
| JP2001267386A |
Foreign References:
| US20060138411 | ||||
| CN104282594A |
Attorney, Agent or Firm:
Kyosei International Patent Office