PURPOSE: To improve the system efficiency to interruption by forming a processing program of cause to interruption as a bank in parallel with a main storage address of a CPU to decrease the ratio of the interruption processing program to the main storage capacity.
CONSTITUTION: A hardware interruption control circuit 2 is connected to a CPU1 of a computer eqipment and a memory selection circuit 5 is connected to the control circuit 2. Further, a CPU main storage section memory 3 and a bank memory 4 are connected to the CPU1 and a memory selection signal 11 from the circuit 5 is fed to the bank memory 4. A hardware interruption signal 6 is inputted to the control circuit 2 and the circuit 5 of the equipment, and when any of the signals 6 is enabled, an interruption signal 7 is fed to the CPU1 and a memory selection control signal 8 is fed to the circuit 5. The circuit 5 selects any of the memories 4 in response to the signal 8 to decrease the ratio of the interruption processing program on the memory 3 thereby improving the system efficiency to interruption.
MIZUKAMI KAZUSHI
SHIBUYA SATOSHI
HITACHI MICROCUMPUTER ENG
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