Title:
COMPUTER OUTPUT DATA PROCESS INTENSIFYING SYSTEM
Document Type and Number:
Japanese Patent JPS5391640
Kind Code:
A
Abstract:
A circuit and method for increasing the output data per unit time from a computer to its associated peripheral terminals or utilization devices is disclosed in which the computer output address and data lines are time multiplexed by a novel decoding technique which enables the address bits and data bits to be interpreted together to form a new data word having a number of bits equal to the sum of the original data bits and the address bits interpreted as data bits. A plurality of decoders, each at a peripheral terminal and each having an identification address code, enable a window for decoding multiple transfers of data on output address and data lines, said window having a predetermined time duration during which all other peripheral identification address codes are locked out, until the data transfer is completed. A microprocessor embodying the invention is also disclosed in which the output data capability is increased from eight to sixteen bits without hardware modification to the microprocessor.
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Inventors:
PAURU JIYONZU KUUPAA
Application Number:
JP14620377A
Publication Date:
August 11, 1978
Filing Date:
December 07, 1977
Export Citation:
Assignee:
NCR CO
International Classes:
G06F13/14; G06F13/28; G06F9/22; G06F13/38; (IPC1-7): G06F3/00; G06F9/16