Title:
COMPUTER SYSTEM DETECTING PARITY ERROR AND OPERATING METHOD THEREFOR
Document Type and Number:
Japanese Patent JP2988501
Kind Code:
B2
Abstract:
PURPOSE: To detect whether or not a parity error occurs to data written or read out between a system bus and an I/O bus.
CONSTITUTION: The computer system having a CPU 38 and a bus including the system bus 76 and I/O bus 32 detects parity errors which possibly occur when data are written between the I/O bus 32 and system bus 76. Once a parity error is detected, the address where the error has occurred is stored and sent out of the system bus 76 to the CPU 38.
Inventors:
NADAA AMINI
BECHARA FUAUATSUDO BORII
SHAAUTSUDO BURANON
RICHAADO RUISU HOON
BECHARA FUAUATSUDO BORII
SHAAUTSUDO BURANON
RICHAADO RUISU HOON
Application Number:
JP32341192A
Publication Date:
December 13, 1999
Filing Date:
December 02, 1992
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
G06F11/07; G06F11/10; G06F13/00; G06F11/22; (IPC1-7): G06F11/10; G06F13/00
Domestic Patent References:
| JP6140645A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)
Previous Patent: METHOD FOR RECYCLING WASTE PHOTOGRAPHIC PROCESSING SOLUTION
Next Patent: VACUUM SEWAGE-COLLECTING SYSTEM
Next Patent: VACUUM SEWAGE-COLLECTING SYSTEM