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Patent Searching and Data


Title:
COMPUTER SYSTEM DETECTING PARITY ERROR AND OPERATING METHOD THEREFOR
Document Type and Number:
Japanese Patent JP2988501
Kind Code:
B2
Abstract:

PURPOSE: To detect whether or not a parity error occurs to data written or read out between a system bus and an I/O bus.
CONSTITUTION: The computer system having a CPU 38 and a bus including the system bus 76 and I/O bus 32 detects parity errors which possibly occur when data are written between the I/O bus 32 and system bus 76. Once a parity error is detected, the address where the error has occurred is stored and sent out of the system bus 76 to the CPU 38.


Inventors:
Nader, Amini
Boury, Bechara Fouad
Brannon, Sherwood
Horne, Richard Louis
Application Number:
JP1992000323411
Publication Date:
December 13, 1999
Filing Date:
December 02, 1992
Export Citation:
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Assignee:
INTERNATL BUSINESS MACH CORP <IBM>
International Classes:
G06F11/07; G06F11/10; G06F13/00; G06F11/22; (IPC1-7): G06F11/10; G06F13/00
Domestic Patent References:
JP6140645A
Attorney, Agent or Firm:
坂口 博 (外1名)