Title:
COMPUTER SYSTEM FOR IRREGULAR EXECUTION OF INSTRUCTIONS
Document Type and Number:
Japanese Patent JP3876033
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To attain plural accesses at low cost to a data cache from a processor and to improve the data throughput by providing such a constitution that the processor simultaneously sends plural addresses to the corresponding cache banks in a single processor cycle.
SOLUTION: A system 80 of a computer which irregularly carries out instructions is provided with a data cache 24 which includes banks 98a and 98b, and a processor which simultaneously sends the addresses to the corresponding banks 98a and 98b in a single processor cycle. These addresses include the odd and even numbered data addresses which are directed by the odd numbered bank 98a and the even numbered bank 98b respectively. The system 80 also has a means 48 that is related to the processor which irregularly carries out the instructions and receives the data addresses based on the irregular instructions.
Inventors:
Greg Resalter
Application Number:
JP1234497A
Publication Date:
January 31, 2007
Filing Date:
January 27, 1997
Export Citation:
Assignee:
HEWLETT-PACKARD COMPANY
International Classes:
G06F9/38; G06F12/08; (IPC1-7): G06F12/08; G06F12/08; G06F9/38
Domestic Patent References:
| JP7325716A | ||||
| JP8036525A | ||||
| JP5173879A | ||||
| JP4057130A | ||||
| JP9244952A | ||||
| JP9244895A | ||||
| JP52125243A |
Foreign References:
| WO1995016952A1 |
Other References:
星野友彦,明らかになり始めたP5の姿,日経バイト,日本,日経BP社,1992年11月 1日,No:105,Pages:226-233
納富昭、外3名,DSN型スーパースカラ・プロセッサ・プロトタイプのロード/ストア・パイプライン,情報処理学会研究報告,日本,社団法人情報処理学会,1991年 1月24日,Vol:91,No:9,(91-ARC-86),Pages:1-8
納富昭、外3名,DSN型スーパースカラ・プロセッサ・プロトタイプのロード/ストア・パイプライン,情報処理学会研究報告,日本,社団法人情報処理学会,1991年 1月24日,Vol:91,No:9,(91-ARC-86),Pages:1-8
Attorney, Agent or Firm:
Next student Okada
Previous Patent: DOUBLE-SIDED ADHESIVE TAPE STICKING DEVICE
Next Patent: SYSTEM FOR HOLDING BAND WIDTH TO MAIN MEMORY
Next Patent: SYSTEM FOR HOLDING BAND WIDTH TO MAIN MEMORY