To start clock interruptions on respective computes at the same place and monitor a fault caused by the same job execution even in a system which uses a time-division OS by monitoring how many instructions a processor executes and generating a clock interruption when the number reaches a set value.

A counter register 10-1 in a processor CPU is so constituted as to set a value by software. When a counter interruption enable/disable register 10-2 sets an enable state and the count value of the instruction execution frequency of the processor CPU reaches the value set in itself, a signal is generated, which is regarded as exceptional N-th notification. Therefore, the clock process start places at respective computation nodes can be all consistent among all the computation nodes. Consequently, the operations at the computation nodes can be performed synchronously while avoiding a state wherein clock generation becomes asynchronous, and fault detection can precisely be performed.