To optimize the read/write operation of an asynchronous dynamic random access memory(SDRAM) which operates at different frequency.

A computer system when initialized decides and stores BIOS data including cock frequencies of all existent memories. A memory clock generator 500 generates a memory clock 1, 2, or 3 matching the clock frequency of a memory to be used from a system clock according to the BIOS data of the memory. A memory control part 206 and a processor control part 202 perform data transfer with the memories, processor, and peripheral devices through a bus by using the generated memory clock.