To reduce the clock skew between a processor and a memory unit by providing a clock buffer which generates a new single-end 'regnerated' clock signal from differential clock signals.

The clock buffer 34 includes an input buffer circuit 36 and a phase-locked loop(PLL) 38. The input buffer circuit 36 receives differential clock signals ck and ck' from a memory controller and generates a single-end reference clock signal ck2 from the differential clock signals ck and ck'. The PLL 38 generates a regenerated clock signal CLK which has substantially the same frequency with the single-end reference clock signal ck2 generated by the input buffer circuit 36 and substantially synchronizes with the single-end reference clock signal. The clock buffer 34 supplies a copy of the clock signal CLK to respective memory devices 32. The operation of the memory devices 32 is synchronized with the clock signal CLK.