Title:
COMPUTER SYSTEM WITH MULTIPLE SPEED SYNCHRONOUS BUS
Document Type and Number:
Japanese Patent JP2533246
Kind Code:
B2
Abstract:
PURPOSE: To operate all components of a bus at the clock speed of an initial bus architecture to keep the downward compatibility of the bus architecture.
CONSTITUTION: A synchronous digital multibit system bus which is provided with one clock route, one master speed indicator route 15, and one slave speed indicator circuit 17, a bus control circuit 22 which mutually exclusively supplies a first clock signal and a second higher-speed clock signal to a clock circuit of this bus, and a master circuit and a slave circuit 16 which are connected to this system bus are included. The master circuit 14 includes a master speed indication circuit which supplies a master speed indicator signal, and the slave circuit 16 includes a slave speed indication circuit, and the bus control circuit 22 supplies the second clock signal if it is indicated that both of the master circuit and the slave circuit can function with different frequencies of the second clock signal.
Inventors:
HAWAADO TOOMASU ORUNOITSUCHI
Application Number:
JP7558291A
Publication Date:
September 11, 1996
Filing Date:
March 15, 1991
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
G06F1/06; G06F1/08; G06F13/00; G06F13/42; (IPC1-7): G06F13/42; G06F1/06
Domestic Patent References:
| JP63276157A | ||||
| JP5428535A |
Attorney, Agent or Firm:
Koichi Tonmiya (5 people outside)