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Title:
COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JP2000148489
Kind Code:
A
Abstract:

To prevent data dependency and to execute a plurality of instructions at the same time.

The process of the computer system comprises an instruction buffer 102 which stores a plurality instructions, a temporary buffer 116 which can have addresses specified with indexes including a plurality of temporary storage locations while each one of the instructions is assigned to one of temporary storage locations and the output corresponding to one specific instruction is stored in the temporary storage location assigned to one specific instruction, a data dependency inspecting means 108 which searches for a dependent instruction stored in an instruction buffer while the input of the dependent instruction depends upon the last instruction being an instruction in the instruction buffer precedent to the dependent instruction in specific order, and a circuit 122 which receives dependency data corresponding to the dependent instruction and uses the dependency data so as to relate the input to the temporary storage location assigned to the last instruction.


Inventors:
GARG SANJIV
IADONATO KEVIN R
Application Number:
JP2000008149A
Publication Date:
May 30, 2000
Filing Date:
March 26, 1993
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
G06F9/30; G06F9/34; G06F9/38; G06F15/00; (IPC1-7): G06F9/38; G06F9/38; G06F9/34
Attorney, Agent or Firm:
Masanobu Ebikawa (7 others)



 
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