To reduce power consumption in a computer system by controlling a period after the generation of an address phase in a peripheral bus for which data from the peripheral bus are shielded inside a power management unit corresponding to a value inside a constitution register.

When a system monitor 204 detects a write cycle to an address required to be shielded inside the power management unit 202 corresponding to the value of the constitution register 209, a power management state machine 206 latches the data from a peripheral connection interface(PCI) bus 220 to the system monitor 204 in a PCI clock cycle following immediately after an address cycle or after one, two or three clock cycles. During the data phase of the PCI cycle, the byte enable signals of the PCI bus 220 are decoded by the system monitor 204 further and a specified byte to be shielded is decided inside the constitution register 209.