CONFIGURABLE INPUT BLOCK AND OUTPUT BLOCK FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK, AND PHYSICAL LAYOUT

Title:

CONFIGURABLE INPUT BLOCK AND OUTPUT BLOCK FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK, AND PHYSICAL LAYOUT

Document Type and Number:

Japanese Patent JP2023139013

Kind Code:

A

Abstract:

To provide an analog neural memory system and method that has an input block and an output block which are configurable and a physical layout and that uses a nonvolatile memory cell.SOLUTION: In a vector matrix multiplication (VMM) system 3400, an input circuit block 3409 (3410) supports different numbers of arrays 3401, 3402 (3403, 3404) arranged in a horizontal direction, and an output circuit block 3411 (3412) supports different numbers of arrays 3401, 3403 (3402, 3404) arranged in a vertical direction.SELECTED DRAWING: Figure 34

Inventors:

TRAN HIEU VAN
STEPHEN TRINH
VU THUAN
STANLEY HONG
VIPIN TIWARI
MARK REITEN
DO NHAN

Application Number:

JP2023109273A

Publication Date:

October 03, 2023

Filing Date:

July 03, 2023

Export Citation:

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Assignee:

SILICON STORAGE TECH INC

International Classes:

G06F12/00; G06F12/06; G06G7/16; G06G7/184; G06G7/60; G11C7/04; G11C7/06; G11C11/54; G11C16/04

Attorney, Agent or Firm:

Patent Attorney Corporation Wisdom International Patent and Trademark Office

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