Title:
CONFIGURATION MEMORY
Document Type and Number:
Japanese Patent JP2015185180
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To propose a nonvolatile configuration memory having a small area.SOLUTION: The configuration memory related to the present embodiment includes: memory cell MC0 comprising a first MISFET Mwhose source and drain on one side are connected to a first bit line LBLand whose gate is connected to a first word line WL_C1 and a second MISFET Mwhose source and drain on one side are connected to a second bit line LBLand whose gate is connected to the first word line WL_C1; and a sense amplifier SA0 connected to the first and second bit lines LBLand LBL. Data are written into the memory cell MC0 by injecting channel hot electrons into a gate insulation layer of the first MISFET Mthereby changing a threshold voltage of the first MISFET Mfrom a first value to a second value and leaving a threshold voltage of the second MISFET Mas the first value.
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Inventors:
TATSUMURA KOSUKE
Application Number:
JP2014058812A
Publication Date:
October 22, 2015
Filing Date:
March 20, 2014
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G11C16/02; G11C16/04; G11C16/06; H01L21/336; H01L21/8247; H01L27/10; H01L27/115; H01L29/788; H01L29/792; H03K19/177
Attorney, Agent or Firm:
Suzue International Patent Office