Title:
CONNECTION DEVICE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH04287347
Kind Code:
A
Abstract:
PURPOSE: To reduce a cell area, by preventing a conductive layer or a substrate located at a lower part from being exposed by an etching stop layer, and connecting a conductive layer to be connected to a lower wiring layer. CONSTITUTION: A contact hole 20 is formed by etching one portion of a second insulation layer 4 and a first insulation layer 2, by utilizing a mask B for etching stop layer for forming an etching stop layer 3A and a contact mask C located in a mask A for wiring for forming a partial wiring 1A. Therefore, the width of the upper part of the contact hole is the minimum width that can be formed from the contact mask pattern process. Also, the lower width is formed to be a smaller width due to the etching stop layer 3A. Therefore, even if the contact hole 20 is formed toward one side surface at the position of the wiring layer 1A, the side surface of the lower wiring layer 1A is etched since the etching stop layer 3A exists, thus preventing another conductive layer at a lower part or a substrate from being exposed.
Inventors:
KIN SAIKOU
Application Number:
JP30432591A
Publication Date:
October 12, 1992
Filing Date:
November 20, 1991
Export Citation:
Assignee:
GENDAI DENSHI SANGYO KK
International Classes:
H01L21/768; H01L23/522; H01L21/3213; (IPC1-7): H01L21/3205; H01L21/90
Domestic Patent References:
| JPS59172744A | 1984-09-29 | |||
| JPS6151972A | 1986-03-14 | |||
| JPS57157546A | 1982-09-29 | |||
| JPH01214046A | 1989-08-28 | |||
| JPH0391929A | 1991-04-17 | |||
| JPH01313959A | 1989-12-19 | |||
| JPS62217635A | 1987-09-25 | |||
| JPS6229169A | 1987-02-07 |
Attorney, Agent or Firm:
Minoru Nakamura (7 outside)