PURPOSE: To minimize the circuit scale when many peripheral circuits are connected to a CPU and to generate the response signal for detecting the end of data transfer operation on a peripheral circuit side by the CPU according to the access time of the peripheral circuit without any circuit alteration.

CONSTITUTION: When the CPU accesses one of the peripheral circuits A-D, a cycle control part reads the wait quantity of an accessed peripheral circuit out of an 8-circuit D flip-flop by respective decoders and a wait quantity setting circuit 16 in a wait quantity retrieval circuit 14, and an ACK signal generating circuit 18 clocks a wait time corresponding to the read wait quantity and outputs a Low-level ACK signal to the CPU.