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Title:
CONSTANT VOLTAGE CIRCUIT AND ITS VOLTAGE OUTPUT CONTROL METHOD
Document Type and Number:
Japanese Patent JP2007334573
Kind Code:
A
Abstract:

To provide a constant voltage circuit for improving input/output voltage characteristics by suppressing the increase in current consumption in a consistent status, and suppressing the rise of an output voltage due to the leak currents of an output transistor and its output voltage control method.

The leak currents of an output transistor M1 flow into resistances R1 and R2 for output voltage detection, and this results in the rise in an output voltage Vo. When an error amplifier circuit 3 increases the gate voltage of an output transistor M1 to an almost input voltage Vdd, the output edge of a comparator 11 is turned into a high level, and an NMOS transistor M11 is turned on and put in a conductive status. A constant current source 12 configuring a pseudo load is connected between an output OUT and a ground voltage, and the lead currents of the output transistor M1 flow through the NMOS transistor M11 and a constant current source 12 to the ground voltage. Thus, it is possible to suppress the rise in the output voltage Vo due to the leak currents of the output transistor M1.

COPYRIGHT: (C)2008,JPO&INPIT


Inventors:
TAKAGI YOSHIKI
Application Number:
JP2006164851A
Publication Date:
December 27, 2007
Filing Date:
June 14, 2006
Export Citation:
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Assignee:
RICOH KK
International Classes:
G05F1/56; H01L21/822; H01L27/04
Domestic Patent References:
JP2000194431A2000-07-14
JPH10301642A1998-11-13
JP2003005848A2003-01-08
JPH10254560A1998-09-25
Attorney, Agent or Firm:
Masahiro Ishino