PURPOSE: To increase working speed, and to improve the degree of integration by forming a plurality of logic units, which have the same logic function and mutually different layout correlation at every same logic unit and marginal trouble fraction defectives of which are reduced, and a majority decision circuit receiving outputs from a plurality of logic units onto a semiconductor wafer.

CONSTITUTION: Each partition 5 on a semiconductor wafer 1 represents logic blocks shaped onto the semiconductor wafer 1. Respective logic block has logic units 2i in required number, a majority decision circuit 4 and a multiplexer 7 at every logic unit. The logical functions of each logic unit 2i are equalized, and correlation is made to differ mutually so that marginal trouble is generated at random in the layouts of the units 2i. The marginal trouble fraction defectives DM of the logic units are selected at a comparatively large value. The multiplexer 7 receives select signals selecting the logic units accepted by a test and is operated. According to the logical blocks by such constitution, the size of a power pattern can be scaled down by reducing the DM, and the size of the logic blocks can be miniaturized. Consequently, wiring length among the logic blocks can be shortened, thus increasing working speed, then also improving the degree of integration.