Title:
エントリデータの入れ替えを高速化したコンテンツ・アドレッサブル・メモリ
Document Type and Number:
Japanese Patent JP4749600
Kind Code:
B2
Abstract:
A contents addressable memory comprises: memory cells arranged in a matrix at positions where word lines extending along a row cross bit lines extending along a column; and search buses extending along the column and match lines extending along the row; and a comparison circuit, provided in each memory cell, comparing data in search bus and data stored in memory cell and outputting comparison result to the match line. Transfer units having a first transfer gate, a transfer cell for temporarily storing data from memory cell, and a second transfer gate are provided between a pair of memory cells arranged along the column. Data from one of pair of memory cells is stored in the transfer cell via first or second transfer gate, then that data stored in transfer cell is stored in other of pair of memory cells via the second or first transfer gate.
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Inventors:
Yanagawa Miki
Application Number:
JP2001162183A
Publication Date:
August 17, 2011
Filing Date:
May 30, 2001
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
G11C15/04; G11C15/00
Domestic Patent References:
| JP6275077A | ||||
| JP3283092A | ||||
| JP4501332A |
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku
Hayashi Tsunetoku