Title:
CONTINUOUS ADAPTATION TYPE PHASE LOCK LOOP SYNTHESIZER
Document Type and Number:
Japanese Patent JPH02189028
Kind Code:
A
Abstract:
PURPOSE: To shorten the time required for lock by coupling a control pulse having a wide(narrow) pulse width to a loop filter at a first (second) electric charge transfer speed and preventing the control pulse having the narrow pulse width from being coupled to the control line input of a voltage controlled oscillator. CONSTITUTION: A pulse 301 which is applied to an up input and has a sufficient pulse width presents a leading edge output pulse 303 to a narrow band filter of a low-speed lock route, and other pulses 305 are directly given to the loop filter. According as the input pulse 301 gets narrower, the principal output from a pulse extraction circuit takes a form of the output pulse 303. This continuous separation of pulses based on the pulse width is used by other parts of the circuit, and the loop filter is charged at two speeds corresponding to a high-speed lock route (wide pulse width) and the low-speed lock route (narrow pulse width). Thus, the time required for lock is shortened.
Inventors:
AREKISANDAA DABURIYU HIITARA
SUTEIIBUN EFU JIRIGU
SUTEIIBUN EFU JIRIGU
Application Number:
JP31050189A
Publication Date:
July 25, 1990
Filing Date:
November 29, 1989
Export Citation:
Assignee:
MOTOROLA INC
International Classes:
H03L7/089; H03L7/10; H03L7/18; H03L7/107; H03L7/183; (IPC1-7): H03L7/107; H03L7/18
Foreign References:
| US4387348A | 1983-06-07 |
Attorney, Agent or Firm:
Yoshiaki Ikeuchi