To provide a control apparatus that can be manufactured at low cost, while reducing malfunctions, and to provide an image forming apparatus.
A control apparatus 30 generates a rise a2 of an output signal Sig2 with a delay of a predetermined time from generation of a rise a1 of an output signal Sig1. The control apparatus includes: a counter 108 for counting numbers from 0 to n-1 at a frequency with cycles of a first period Tc; a CPU 100 that operates at a frequency with cycles of a second period Tr that is longer than the first period Tc, and calculates a remainder 1 of a division by adding a number of counts of the counter 108 corresponding to the predetermined time t to a count value of the counter 108 at the time of generation of the rise a1 and by dividing a result of the addition by n; and an output section 106 for outputting the second rise a2 at a time when the count value of the counter 108 becomes equal to the remainder N1.
NAKANO NORIHIKO
WATANABE HIROYUKI
TAMURA TOMONOBU
| JPH02165721A | 1990-06-26 | |||
| JPH04122151A | 1992-04-22 | |||
| JPH0589261A | 1993-04-09 | |||
| JPH03128529A | 1991-05-31 | |||
| JPS63192927A | 1988-08-10 | |||
| JP2007069357A | 2007-03-22 | |||
| JP2004279188A | 2004-10-07 |
Tani Kazuhiro