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Patent Searching and Data


Title:
CONTROL CIRCUIT FOR MULTIPLEXED ARITHMETIC AND LOGIC UNIT
Document Type and Number:
Japanese Patent JPS5827249
Kind Code:
A
Abstract:

PURPOSE: To continue the execution of a microprocessor by using the outputs of a normal multiplex device and to prevent a titled circuit from the regeneration of errors by comparing outputs of the multiplexing device to demarcate faults.

CONSTITUTION: Data from registers 1, 2 are inputted to arithmetic and logic units (ALU) 31, 32 and outputs from respective units are inputted to a comparator 4 and an output switching circuit 5, respectively. A collated result is outputted from the comparator 4 and, if the result is normal, a control circuit 6 is actuated and the output switching circuit 5 adop an output from one previously fixed unit, the ALU31 or ALU32, and sends the output to a data bus D-BUS. When a fault is detected by the comparator 4, a diagnosing means is executed by an output signal from a starting circuit 7 and either of the normal units, ALU31 or ALU32, is discriminated. The control circuit 6 actuates the output switching circuit 5 by said discriminated signal and sends an output result form the normal ALU31 or ALU32 to the D-BUS.


Inventors:
TANIYAMA YUKIO
WADA TADAHIRO
Application Number:
JP12458481A
Publication Date:
February 17, 1983
Filing Date:
August 08, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/20; G06F11/16; (IPC1-7): G06F11/20
Attorney, Agent or Firm:
Koshiro Matsuoka