PURPOSE: To generate a synchronizing (SYNC) pattern in an 8-10 conversion circuit at a prescribed period by preparing dummy data in an 8-bit data array at a part corresponding to a point of time that the SYNC pattern is to be generated, forming a means for generating a signal '1' in accordance with an address value indicating the positions of the dummy data in a buffer memory and connecting the output of the signal generating means to the SYNC/DATA terminal of the 8-10 conversion circuit.

CONSTITUTION: A latch circuit 24 has eight cells corresponding to the number of bits. A shift register 26 holds 10-bit data to be an output of the 8-10 conversion circuit 10 and sends the 10-bit data to an NRZI conversion circuit as serial data. A column address line 28 and a row address line 30 from an address control circuit 22 to a memory 20 are connected to a SYNC/DATA control circuit 32 and the output of the control circuit 32 is connected to the SYNC/ DATA terminal of the circuit 10. When the column and row address lines 28, 39 indicate a memory cell to generate the SYNC pattern, the control circuit 32 generates an output '1'.