PURPOSE: To eliminate the timing control in the write/read control of the RAM, by controlling the writing and detection with the clock pulses of different phases.

CONSTITUTION: The clock pulse generator CP2 generates two types of clock pulses of different phases by the outputs Q and Q' of the FF which works in response to the oscillator OSC2. One of the two clock pulses controls the write control circuit WC2 and the writing data circuit IC2 to perform a writing to the RAM. In the same way, the other clock pulse controls the reading of the RAM. Thus the write/read of the RAM is controlled without timing control and by the clock pulses that have no interference to each other. As a result, a timing control circuit can be eliminated, at the same time secuirng a simultaneous control for both the writing and reading.