PURPOSE: To synchronize two video signals to each other with a simple constitution, by generating a gate pulse having a pulse width of about 0.5H by using a signal which is generated by delaying a vertical synchronizing signal separated from a video signal A to be used as a reference by a synchronizing signal separating circuit, and generating a displaying timing control signal by a delay circuit and single pulse generating circuit when a synchronizing signal separated from the other video signal B and the horizontal synchronizing signal of the video signal A do not coincide with each other in terms of phase.

CONSTITUTION: When the timing of the vertical synchronizing signal VB of a video signal B coincides with another video signal A under a synchronous condition, no trigger pulse is generated in the output HA, of an AND circuit 16, but, when the phase of the vertical synchronizing signal VB does not coincide, a trigger pulse HA, synchronous to a horizontal synchronizing signal HA is generated in the output HA, of the AND circuit 16. When an asynchronous condition is detected and the trigger pulse HA, is generated from the AND circuit 16, the 2nd single pulse generating circuit 18 is triggered after delaying the trigger pulse HA, by a prescribed delay time by means of the 2nd delay circuit 17 and a displaying timing control signal of a prescribed pulse width is generated. The generated control signal is supplied to the displaying timing control circuit of a display driving device and a signal generating timing is initialized so that the vertical synchronizing signal VB coincides with the synchronous condition of the video signal A.