Title:
CONTROL METHOD FOR CLOSELY COUPLED MULTIPROCESSOR SYSTEM, CLOSELY COUPLED MULTIPROCESSOR SYSTEM AND STORAGE MEDIUM THEREFOR
Document Type and Number:
Japanese Patent JP3239935
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a closely coupled multiprocessor system for evading sub stantial processing performance decline.
SOLUTION: For this closely coupled multiprocessor system, plural processors 102 and 107 provided with cache memories 101 and 106 are respectively connected to a bus 111 through processor controllers 103 and 108 and the respective processor controllers 103 and 108 are provided with copy tag memories 104 and 109 storing the tag information of the cache memories. In this case, the respective processor controllers 103 and 108 hold the address of the tag information in a register in the case of detecting a parity error in the tag information read from the copy tag memories 104 and 109, and in the case of detecting the parity error again in the tag information read from the copy tag memories, compare the address of the tag information with the address held in the register, inhibit the use of the copy tag memory in the case that the two addresses do not match and inhibit only the use of the address in the case that the two addresses match.
Inventors:
Hidekazu Uehara
Application Number:
JP32883197A
Publication Date:
December 17, 2001
Filing Date:
November 28, 1997
Export Citation:
Assignee:
NEC
International Classes:
G06F12/16; G06F15/16; G06F12/08; G06F15/177; (IPC1-7): G06F12/08; G06F12/16
Domestic Patent References:
| JP4124747A | ||||
| JP52130244A | ||||
| JP5279736A |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)