Title:
CONTROL SIGNAL GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPH04195604
Kind Code:
A
Abstract:
PURPOSE:To obtain a control signal generating circuit which has a small circuit scale by storing a period wherein the same signal value continues as memory data in a RAM, inverting the signal value at the end of the period where the same signal value continues and generating a control signal, and removing the redundancy of the memory data. CONSTITUTION:The control signal is generated by holding a reset signal at '1' and a down counter 3 with a load begins to count down. The output of the down counter 3 with the load becomes '0' 100 cycles of a clock later and the output of a 0 detector 4 varies from '0' to '1'; and the counter 1 counts up and the control signal is switched from '0' to '1'. At this time, the counter 1 accesses memory data in an address 1 of the signal variation point recording ROM 2 and 50 indicating a period wherein the control signal is '1' is loaded in the down counter 3 with the load. This operation is repeated to generate the control signal with the memory data. Consequently, the redundancy of the memory data can be removed and the control signal generating circuit with the small circuit scale is obtained.
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Inventors:
UEDA TOSHIHIRO
Application Number:
JP33537990A
Publication Date:
July 15, 1992
Filing Date:
November 28, 1990
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G05B19/02; (IPC1-7): G05B19/02
Attorney, Agent or Firm:
Masuo Oiwa (2 outside)