Title:
カウンタ回路を備える制御信号生成回路ならびに表示装置
Document Type and Number:
Japanese Patent JP4763049
Kind Code:
B2
Abstract:
In a counter circuit of a control signal generating circuit, a selector circuit selects under control which is in accordance with a selector circuit control signal (CTR) a predetermined one in a signal VSYNC and a signal HSYNC, which are pulse signals, so as to input a pulse signal thus selected to a counter. The counter outputs a counted result of pulses of the inputted pulse signal. By use of the counted result, a VSYNC synchronization signal generating circuit or an HSYNC synchronization signal generating circuit generates a control signal to control the driving of image display.
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Inventors:
Yousuke Nakagawa
Application Number:
JP2008516568A
Publication Date:
August 31, 2011
Filing Date:
February 20, 2007
Export Citation:
Assignee:
Sharp Corporation
International Classes:
H03K23/40; G02F1/133; G09G3/20; G09G3/36
Domestic Patent References:
| JPH02188017A | 1990-07-24 | |||
| JP2001136059A | 2001-05-18 |
Attorney, Agent or Firm:
Kenzo Hara International Patent Office