PURPOSE: To improve easily the efficiency of data transfer by providing the first- in/first out FIFO function to a buffer memory for data transfer together with the function to which a random access is possible directly from a microprogram.
CONSTITUTION: A switch SW which is connected to a buffer memory BM and a data bus MDB for microprocessor is connected to a data bus DB. A write/read pointer WRP of the BM is connected to a selection circuit SEL, and the output of the circuit SEL is turned into the address signal of the BM. The whole part is controlled by a microprogram stored in a control memory CM. The memory BM stores temporarily the read/write data in an FIFO style, and a direct access is possible to the BM from a microprocessor MP. Furthermore the pointer WRP is also capable of the direct reading and writing.
OOTANI AKIO
JPS5436140A | 1979-03-16 | |||
JPS54107231A | 1979-08-22 | |||
JPS54115036A | 1979-09-07 | |||
JPS57134748A | 1982-08-20 |