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Title:
CONTROL SYSTEM FOR FILE MEMORY
Document Type and Number:
Japanese Patent JPS607521
Kind Code:
A
Abstract:

PURPOSE: To improve easily the efficiency of data transfer by providing the first- in/first out FIFO function to a buffer memory for data transfer together with the function to which a random access is possible directly from a microprogram.

CONSTITUTION: A switch SW which is connected to a buffer memory BM and a data bus MDB for microprocessor is connected to a data bus DB. A write/read pointer WRP of the BM is connected to a selection circuit SEL, and the output of the circuit SEL is turned into the address signal of the BM. The whole part is controlled by a microprogram stored in a control memory CM. The memory BM stores temporarily the read/write data in an FIFO style, and a direct access is possible to the BM from a microprocessor MP. Furthermore the pointer WRP is also capable of the direct reading and writing.


Inventors:
SASAMOTO YOSHIFUMI
OOTANI AKIO
Application Number:
JP11362783A
Publication Date:
January 16, 1985
Filing Date:
June 25, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F3/06; G06F5/06; G06F13/38; (IPC1-7): G06F3/06
Domestic Patent References:
JPS5436140A1979-03-16
JPS54107231A1979-08-22
JPS54115036A1979-09-07
JPS57134748A1982-08-20
Attorney, Agent or Firm:
Ashida Tan



 
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