Title:
CONTROL SYSTEM FOR NAND TYPE FLASH MEMORY
Document Type and Number:
Japanese Patent JP2008158991
Kind Code:
A
Abstract:
To use a control board in a long life cycle without deteriorating functions or spec by enabling an NAND type flash memory controller to correspond to various NAND type flash memories.
A main CPU is started by turning on a system power source, and an NAND type flash memory controller 12 is started. In starting the NAND flash memory controller 12, an NAND ID 20 is read from the NAND type flash memory 13, and individual specifications necessary for memory access are set, and configuration data 21 are read, and a speed (access time) when memory access is set. Then, user data 22 of the NAND type flash memory 13 are copied to a DRAM, and a main program is executed by the main CPU.
Inventors:
AIHARA TAKESHI
Application Number:
JP2006350203A
Publication Date:
July 10, 2008
Filing Date:
December 26, 2006
Export Citation:
Assignee:
RICOH KK
International Classes:
G06F12/06; G06F12/00; G11C16/02
Domestic Patent References:
JP2005301831A | 2005-10-27 | |||
JP2006331233A | 2006-12-07 |
Foreign References:
WO2006101123A1 | 2006-09-28 |
Attorney, Agent or Firm:
Hiroaki Sakai
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