Title:
制御システム
Document Type and Number:
Japanese Patent JP6926821
Kind Code:
B2
Abstract:
To provide technology capable of contributing for suppression of malfunction phenomenon and expansion tendency of input/output stand-by time.SOLUTION: In a control system 1, a control circuit comprising a state output unit 2 taking a logical sum and a signal output unit 3 taking a logical product is configured to be able to control a data processing device 4 to one of the reset state and the reset release state. The state output unit 2 detects a lock status signal SS indicating whether a clock signal CS is in the lock state or the unlock state and a logical product output signal 3S of the signal output unit 3 to output a logical sum output signal 2S. The signal output unit 3 detects a reset signal RS generated at a reset circuit 6 and the logical sum output signal 2S output from the state output unit 2 to output the logical product output signal 3S. Then, the logical product output signal 3S of the signal output unit 3 is input to the data processing device 4.SELECTED DRAWING: Figure 1
Inventors:
Kazushi Ono
Application Number:
JP2017161704A
Publication Date:
August 25, 2021
Filing Date:
August 25, 2017
Export Citation:
Assignee:
KABUSHIKI KAISHA MEIDENSHA
International Classes:
G06F1/24
Domestic Patent References:
| JP2002335156A | ||||
| JP11136109A | ||||
| JP2000305655A | ||||
| JP2014068124A |
Attorney, Agent or Firm:
Hiromichi Kobayashi
Tomioka Kiyoshi
Uzawa Hidehisa
Tomoyuki Ota
Tomioka Kiyoshi
Uzawa Hidehisa
Tomoyuki Ota