PURPOSE: To make high-frequency operation possible with a signal transfer time lag lessened by supplying input signals without interposing any gate circuit.
CONSTITUTION: Circuit 31 of the 1st stage is constituted by connecting P-type FET34 between electric power source VDD and output terminal A and N-type FET35∼37 between point A and the earth point, and circuit 32 of the 2nd stage is also constituted by connecting P-type FET38 and 39 between VDD and output terminal B and N-type FET40 and 41 between terminal B and the earth point. Further, circuit 33 of the 3rd stage is constituted by connecting P-type FET42 between VDD and output terminal C and N-type FET43∼45 between terminal C and the earth point. Then terminals C, A and B are connected to gates of FET34 and 35, 39 and 40, and 43 respectively to frequency-divide clock signal CK supplied to gates of FET36 and 44. The output of the frequency division is led to terminal Q to obtain a frequency a half that of clock signal CK.
SUZUKI YASOJI
ICHIYANAGI TAKESHI
