To provide a controller for CPU operation speed capable of stably controlling the operator speed of a CPU, and surely reducing increase in the temperature of the CPU.

This controller is constituted of a CPU 10, a temperature controller 20 for detecting the temperature of the CPU or the neighboring area, and for outputting a trigger signal when the detected temperature is matched with any of two trigger temperatures set at two points, and a clock frequency generating circuit 30 for outputting a clock signal to the CPU. When the trigger signal is inputted from the temperature controller, the CPU changes the frequency of the clock signal according to the detected temperature, and updates the trigger temperatures of the temperature controller at two points to the trigger temperature lower than the detected temperature and the trigger temperature higher than the detected temperature. Those newly set trigger temperatures at two points include the present detected temperature of the temperature controller between them so that even when the temperature of the CPU increases, reaches the trigger temperature, and decreases, or the temperature of the CPU decreases, reaches the trigger temperature, and increases, the temperature control of the CPU can be continuously carried out.