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Patent Searching and Data


Title:
CONTROLLER AND DEVICE APPARATUS
Document Type and Number:
Japanese Patent JP2013156731
Kind Code:
A
Abstract:

To provide a controller for transmitting SDB (Set Device Bits) FIS (Frame Information Structure) after the completion of data transfer based on an FPDMA (First Party Direct Memory Access) command.

The controller includes: a command completion recognition part 33 for recognizing that it is possible to transmit an SDB FIS after the completion of data transfer based on an FPDMA command which is being currently executed between itself and a host device; an R_RDY response suppression control signal generation part 35 for generating an R_RDY response suppression control signal on the basis of the recognition result of the command completion recognition part; an R_RDY response suppression part 41 for making no R_RDY response to an X_RDY from the host device on the basis of the R_RDY response suppression control signal; and an SDB FIS transmission part 34 for transmitting the SDB FIS to the host device after the R_RDY response suppression control.


Inventors:
ABE YUICHI
KOFUCHI MASAKI
SAKAMOTO MIYABI
Application Number:
JP2012015116A
Publication Date:
August 15, 2013
Filing Date:
January 27, 2012
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G06F13/10
Attorney, Agent or Firm:
Hiroaki Sakai