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Title:
CONTROLLING DEVICE OF DIRECT MEMORY ACCESS
Document Type and Number:
Japanese Patent JPS59108135
Kind Code:
A
Abstract:

PURPOSE: To eliminate the border address between banks at a time on the way of DMA transfer and to switch the banks normally by advancing a transfer starting address at the initial transfer more forward than the leading address of a working area.

CONSTITUTION: It is supposed that the (FD 40) 16 or after of a memory are set up as a usable working area and data are transferred by DMA by dividing the data into 4 times in each 256 bytes. A CPU executes prescribed operation at a step 3 and advances the transfer starting address of the initial DMA transfer more forward than the leading address of the usable working area and fixed on (FEOO) 16 so that a transfer end address is set up to (FFFF) 16, the bank border address, at the end of any one of DMA transfer times of the 2nd, 3rd and 4th. Consequently, the border address between the banks is not generated at a time on the way of the transfer.


Inventors:
SAKAMOTO KEIJI
Application Number:
JP21962882A
Publication Date:
June 22, 1984
Filing Date:
December 14, 1982
Export Citation:
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Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
G06F13/28; (IPC1-7): G06F3/00
Attorney, Agent or Firm:
Shigenori Wada



 
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