Title:
メモリ・アクセスにおける保護タグ・チェックの制御
Document Type and Number:
Japanese Patent JP7291149
Kind Code:
B2
Abstract:
An apparatus comprises address translation circuitry to perform a translation of virtual addresses into physical addresses in dependence on stored page table mappings between the virtual addresses and the physical addresses. The stored page table mappings comprise tag-guard control information. The apparatus comprises memory access circuitry to perform a tag-guarded memory access in response to a target physical address, the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target physical address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target physical address. The memory access circuitry is arranged to perform a non-tag-guarded memory access to the addressed location in response to the target physical address without performing the guard-tag check in dependence on the tag-guard control information.
More Like This:
| JPH02231659 | EXCEPTIONAL ADDRESS DETECTOR |
| JP2005174123 | DISPLAY SYSTEM |
| JP3765145 | ELECTRONIC INFORMATION DISTRIBUTION METHOD |
Inventors:
Burns, Graeme
Application Number:
JP2020540269A
Publication Date:
June 14, 2023
Filing Date:
January 25, 2019
Export Citation:
Assignee:
Arm limited
International Classes:
G06F12/14; G06F9/34; G06F12/0895; G06F12/1009; G06F12/1027
Domestic Patent References:
| JP2009516310A | ||||
| JP6095972A |
Foreign References:
| US20160371179 | ||||
| US20170177429 | ||||
| US5737575 | ||||
| US20070157003 |
Attorney, Agent or Firm:
Patent Attorney Corporation Asamura Patent Office