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Patent Searching and Data


Title:
CONTROLLING SYSTEM OF BUFFER STORAGE DEVICE
Document Type and Number:
Japanese Patent JPS581874
Kind Code:
A
Abstract:

PURPOSE: To prevent the deterioration of the bit factor when an access is given from a CPU, by writing the data of a main storage device requested by a channel into a specific block of a buffer memory which is shared by the CPU and the channel.

CONSTITUTION: The information of a mainstorage device requested by a channel is written into a specific block of the way No.0 of a buffer storage device through an NAND gate 10 haing its output set at a high level with application of a high level requester signal Di given via a channel controller and a low level output of an AND gate 9. On the other hand, the blocks of way Nos. 1W3 are selected via a replace algorism 7 and in accordance with a request given from a CPU sharing the buffer storage device. Thus the information required by the CPU is not stored in the buffer storage device to prevent the deterioration of the hit factor. Accordingly the calculation processing speed is not lowered.


Inventors:
TOYOKI NORIYUKI
Application Number:
JP10013581A
Publication Date:
January 07, 1983
Filing Date:
June 27, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F12/08; G06F13/38; (IPC1-7): G06F3/00; G06F13/00; G11C9/06
Attorney, Agent or Firm:
Kyotani Shiro