To provide a parallel/series conversion circuit capable of realizing a parallel/series conversion using the signal wiring delays and a simple logic circuit.

The parallel/series conversion circuit uses the transmission lines as the different delay elements when parallel signals 1-1 inputted through an input unit 1-2 are transmitted through the transmission lines whose number is corresponding to that of the parallel signals 1-1, and is equipped with a delay unit 1-3 which outputs a plurality of delay element outputs different from each other in delay time and a logic circuit 1-4 which puts together the delay element outputs from the delay unit 1-3 to output series signals to an output unit 1-5.