To provide an A/D conversion of a successive approximation type that decreases a conversion error by suppressing movement of electric charges at switch changeover.

The same circuit configuration of a switch S3A for connecting an internal node NI to a reference voltage VR for charging period to charge up a difference voltage between an analog input voltage AI and the reference voltage VR to a plurality of capacitors C1 to Cn is adopted for the circuit configuration of a switch S4A for canceling a gate overlap capacitance between a gate and a drain of a MOS transistor for configuring the switch S3A. Further, a dimension of the MOS transistor of the switch S3A is set twice the dimension of a MOS transistor of the switch S4A, when the MOS transistors are turned on, the circuit is configured such that bulks of the MOS transistors are connected to an output terminal OUT, that is, the internal node NI.