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Title:
A/D CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JP2020025223
Kind Code:
A
Abstract:
To provide an A/D conversion circuit that can easily configure a clock generation circuit that generates a large number of sampling clocks even when design rules have become finer.SOLUTION: Each of a plurality of connected third-stage inverters Inv1 to Inv8 includes an n-channel transistor Mn and a p-channel transistor Mp. These inverters Inv1 to Inv8 are configured such that the number ratio of the number of gates connected in parallel to the n-channel transistor Mn and the number of gates connected in parallel to the p-channel transistor Mp is different.SELECTED DRAWING: Figure 3

Inventors:
WATANABE TAKAMOTO
Application Number:
JP2018149403A
Publication Date:
February 13, 2020
Filing Date:
August 08, 2018
Export Citation:
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Assignee:
DENSO CORP
International Classes:
H03M1/60; H03K5/15; H03K7/04
Domestic Patent References:
JP2004007385A2004-01-08
JP2005197622A2005-07-21
JP2000036582A2000-02-02
Foreign References:
WO2018063517A12018-04-05
Attorney, Agent or Firm:
Patent Business Corporation Sato International Patent Office