Title:
PARALLEL/SERIAL CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JP3334466
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide the parallel/serial conversion circuit from which data of a stable serial signal are outputted.
SOLUTION: When parallel signal data are received by a data input terminal DATA, the data are latched and inverted by a leading of a latch clock signal received by a latch clock signal input terminal RCK. Then the data are counted based on a clock signal received by the clock input terminal CLK1 and when the count reaches a prescribed value, a ripple carry signal is outputted from a ripple carry signal output terminal RCY. A D flip-flop circuit 2 keeps an output of a serial signal received at a data input terminal D from a data output terminal OUT till the ripple carry signal is received by a reset terminal R.
Inventors:
Hisaharu Ito
Application Number:
JP34065695A
Publication Date:
October 15, 2002
Filing Date:
December 27, 1995
Export Citation:
Assignee:
MATSUSHITA ELECTRIC WORKS,LTD.
International Classes:
G06F5/00; H03M9/00; (IPC1-7): H03M9/00
Domestic Patent References:
| JP63222514A | ||||
| JP2131011A |
Attorney, Agent or Firm:
Junji Ando (1 person outside)
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