PURPOSE: To realize data transfer with an integrated circuit network consisting of 2 systems or above with different data transfer speed by providing a general- purpose input/output terminal selected by a selector to receive a timing clock in addition to a timing clock terminal.

CONSTITUTION: When a selector 114 selects the general-purpose input/output terminal 15, if nothing is outputted to a timing clock bus 2, since no timing clock is given to an integrated circuit, a parallel/serial conversion circuit 11 in the inside is not operated. On the other hand, since the level of a shift clock line 112 and a timing clock bus 6 go to the same level, data is transferred with a respective parallel/serial conversion circuit 11 in integrated circuits 1, 7 according to the clock outputted to the timing clock bus 6. When the selector 114 selects a timing clock terminal 12 inversely, data is transferred in the circuits 1, 5 according to the clock outputted to the bus 2. Thus, the data transfer in the integrated circuit network consisting of two systems or above with different data transfer speeds is realized.